In general, a well region in a flash memory device is formed through the process by which ions are implanted into a semiconductor substrate and are diffused by thermal process. However, the diffused well region formed by this method has the following drawbacks.
Firstly, the diffused well region has a high well resistance of several .OMEGA..about. several hundreds K.OMEGA.. Thus, there is a drawback in the erase speed due to delay time RC. This provides the flash memory device with the cause of defeat in competing the speed with DRAM or SRAM.
Secondly, it has a high parasitic capacitance. Most of the flash cells use a triple P-well structure. The reason is to reduce the resistance of the well, by performing erase operation by which a bias is applied to the well in the flash cell. The operating speed of the device is higher as the delay time (=RC) is smaller. However, as some time taken to charge the parasitic capacitance of this structure itself is required, this affects the major cause slowing the operating speed of the device. This causes a problem that a given level of voltage must be maintained in order to charge the parasitic capacitance. Also, it is one of the most important problems in designing a flash memory device such as a charge pump size in a low-voltage flash memory device design.
Thirdly, there is a problem in the erase speed. The smallest unit of erase in the conventional flash cell is a block (or sector) unit, wherein one block is typically 512 Kbits. That is, the conventional flash memory device can be programmed in one cell unit but could not be erased in one cell unit. Also, as the conventional flash memory device could not be erased in one cell unit, it must be erased in one block unit. Thus, when the erase operation is performed, various problems are generated due to a surplus current flowing into a bit line. There is a difficulty in a design for reducing this bit line current.